1. Field of the Invention
The present invention relates to a semiconductor substrate and semiconductor device and processes of production of the same, more particularly relates to a semiconductor substrate having a silicon on insulator or semiconductor on insulator (SOI) structure (hereinafter also referred to as an SOI substrate) comprising a substrate having a semiconductor layer on an insulating film and a semiconductor device and processes of production relating to the same.
2. Description of the Related Art
Along with the higher integration and higher performance of large-scale integrated circuits (LSI) mounting metal-oxide-semiconductor field effect transistors (MOSFET), semiconductor devices having an SOI structure have been attracting attention.
In an SOI structure, complete element isolation is achieved by a silicon oxide or other insulating film, so software error and latch up are suppressed and a high reliability is obtained even in an LSI having a high degree of integration. Further, since the junction capacity of a diffusion layer can be reduced, there is less electric charging and electric discharging relating to switching, so there is the advantage of a higher speed and a electric lower power consumption.
Several proposals have been made up to now for the process of production of an SOI substrate. There are for example separation by implanted oxygen (SIMOX) and direct bonding such as plasma assisted chemical etching (PACE), bond and etchback SOI (BESOI), polishing a rear surface after bonding as disclosed in Japanese Patent Laid-open No. Hei 10-199840, and a hydrogen ion implantation (smart cut).
In SIMOX, it is relatively easy to make the SOI layer thin, but high concentration oxygen ions are implanted with a high energy, therefore there is the problem that the cost of ion implantation becomes high. Further, remarkable damage of the crystallinity of the silicon semiconductor layer, deterioration of performances of the transistors and other semiconductor elements, and further variations in the thickness of the oxide film in minute regions have been reported. Further, problems such as leakage are manifested along with the reduction of the thickness of the SOI layer.
Further, direct bonding is put to practical use for SOI substrates having SOI layers with thicknesses of 1 to 10 xcexcm.
In PACE, there is a limit in the precision of polishing to eliminate damage, so it is difficult to make the SOI layer thin. Further, since two silicon semiconductor substrates are used, there is the problem of a high manufacturing cost.
In BESOI, ELTRAN (epitaxial layer transfer) using porous silicon obtained by anode oxidation has been developed in recent years. The thickness of the SOI layer is considerably reduced, but there is a problem in the productivity and the supply is unstable. Further, since two silicon semiconductor substrates are also used in this process, the problem of high manufacturing costs remains.
In smart cut, the silicon semiconductor substrate can be reused after peeling, so the manufacturing costs can be suppressed.
Next, an explanation will be made of the process of production of an SOI substrate by smart cut by referring to the drawings.
First, as shown in FIG. 9A, for example, silicon oxide is stacked to a thickness of 200 to 400 nm on a first silicon semiconductor substrate (first substrate) 10 by chemical vapor deposition (CVD) or thermal oxidation to form an insulating film 20.
Next, as shown in FIG. 9B, for example hydrogen ions D are implanted to form a peeling surface 11 in a region at a predetermined depth of the first substrate 10.
Here, the depth of the peeling surface 11 is set to the required thickness of the SOI layer and the thickness of the damage layer (about 200 nm in practice) considering damage at the time of peeling.
Next, the insulating film 20 is polished by for example CMP to flatten the surface.
In this CMP, the insulating film is polished to a surface roughness of a level of 0.4 nm by polishing using a polishing pad made of for example urethane foam or a nonwoven fabric continuous foam and colloidal silica having an average particle size of 40 nm as a polishing slurry to thereby obtain a bondable surface.
Next, as shown in FIG. 9C, a second silicon semiconductor substrate (second substrate) 30 is bonded above the insulating film 20 formed on the first substrate 10. Here, in the figure, the first substrate 10 formed with the insulating film 20 drawn upside down compared with FIG. 9B.
At the time of bonding, in the same way as the first substrate 10, the surface of the second substrate is polished to a surface roughness of a level of 0.4 nm in advance by polishing using a polishing pad made of urethane foam etc. and colloidal silica having an average particle size of 40 nm as the polishing slurry to thereby form a bondable surface. Further, the bonding surfaces, that is, the insulating film 20 surface of the first substrate 10 and the surface of the second substrate 30, are washed (to remove particles on the bonding surfaces) and made hydrophilic (to introduce OH groups into the bonding surfaces) by washing by a mixed washing solution of ammonia water, hydrogen peroxide, and high purity water (NH3:H2O2:H2O=1:2:7). This enables stabilization of the bonding.
Next, as shown in FIG. 10A, first the bonding surfaces are heat treated at about 400xc2x0 C. in an oxygen or inert gas atmosphere to increase the bonding strength, then are further heat treated at about 600xc2x0 C. to peel off the first substrate 10b while leaving the semiconductor layer 10a on the insulating film 20 at the peeling surface 11.
The first substrate 10b can be recovered, flattened at its surface, then routinized as the first substrate or another semiconductor substrate.
In order to further raise the bonding strength of the bonding surfaces of the second substrate 30 and the insulating film 20, for example, it is preferable to heat treat them for about 30 minutes to 2 hours at a temperature of 800 to 1100xc2x0 C. Where an impurity, for example, boron, has been already introduced into the semiconductor layer 10a, preferably the heat treatment is carried out at a low temperature of about 800xc2x0 C. in order to prevent diffusion.
Next, as shown in FIG. 10B, for example CMP is used to polish the semiconductor layer 10a by 200 nm, corresponding to the damage layer, to eliminate the damage at the time of peeling and flatten the surface of the semiconductor layer to obtain the intended SOI substrate.
In this CMP, polishing is applied using for example a nonwoven fabric type continuous foam or urethane foam as the polishing pad and using colloidal silica having an average particle size of 40 nm or an ethylene diamine solution as the polishing slurry so as to obtain the surface roughness and the SOI layer thickness required for the LSI device.
Summarizing the problems to be solved by the invention, in the process of production of an SOI substrate by hydrogen ion implantation (smart cut), due to the limited precision of the polishing step for eliminating the damage layer, the thickness of the SOI layer can only be reduced to about 100 nm. Therefore, when the semiconductor device is miniaturized and the design rule becomes 0.1 xcexcm, the demanded reduction of the thickness of the SOI layer to about 30 to 50 nm cannot be realized.
In the method of polishing the rear surface after bonding disclosed in Japanese Patent Laid-open No. Hei 10-199840, the semiconductor substrate is formed by forming a film acting as a stopper of the polishing, bonding the silicon semiconductor substrates, then polishing the rear surface, but the film acting as the stopper of the polishing is formed with a specific pattern such as the pattern of the element isolation insulating film. Therefore there is the problem in that a general purpose SOI substrate cannot be formed.
Further, in this method, two silicon semiconductor substrates are used, so there is the problem of high manufacturing costs. Further the thick silicon semiconductor substrate must be polished from the rear surface, so there is the problem of variation of the thickness of the SOI layer depending on the polishing precision.
An object of the present invention is to provide a semiconductor substrate having an SOI structure suitable for general purpose use even through structured isolating an SOI layer by an insulating film.
Another object of the present invention is to provide a process of production of a semiconductor substrate of an SOI structure which enables a reduction of the thickness of the SOI layer and enables suppression of the manufacturing costs and variation of the SOI layer thickness.
Still another object of the present invention is to provide a semiconductor device using the above semiconductor substrate.
Still another object of the present invention is to provide a process of production of such a semiconductor device.
To attain the first object, according to a first aspect of the present invention, there is provided a semiconductor substrate for forming a circuit pattern of a semiconductor chip, comprising a substrate, an insulating film formed on the substrate, and a semiconductor layer formed on the insulating film, the semiconductor layer being isolated by the insulating film for every region of formation of a circuit pattern of a semiconductor chip.
Preferably, a conductive film is formed in the insulating film in a lower portion of the semiconductor layer.
According to this aspect of the invention, despite the semiconductor substrate being one for forming a circuit pattern of a semiconductor chip having a semiconductor layer on an insulating film formed on a substrate, since the semiconductor layer is isolated by the insulating film for every region of formation of a circuit pattern of a semiconductor chip, it is not limited to a special element isolation pattern. Even if a structure where a semiconductor layer having an SOI structure is isolated by an insulating film is employed, it is possible to apply the same for general purpose use.
To attain the second object, according to a second aspect of the present invention, there is provided a process of production of a semiconductor substrate having a semiconductor layer on an insulating film formed on a substrate, comprising the steps of forming a groove of a predetermined depth having a predetermined pattern in a first substrate made of a semiconductor, forming a first insulating film in the groove and above the first substrate, doping an impurity for peeling off the first substrate into a region of a predetermined depth of the first substrate, bonding a second substrate from above the first insulating film, removing the first substrate in the region with the impurity doped therein by heat treatment while leaving the semiconductor layer of the surface layer of the first substrate on the first insulating film, and polishing the semiconductor layer using as a stopper the surface of the first insulating film shaped projecting out at a bottom of the groove.
Preferably, the step of forming the groove includes a step of forming a groove of a predetermined depth in an outer circumferential region of the circuit pattern of the semiconductor chip formed in the semiconductor layer.
Preferably, the step of forming the groove includes a step of determining the depth of the groove so that the thickness of the semiconductor layer obtained after the step of polishing the semiconductor layer becomes a predetermined thickness.
Preferably, the step of forming the first insulating film includes a step of forming the first insulating film by an insulating material with a polishing rate slower than the first substrate.
More preferably, a silicon semiconductor substrate is used as the first substrate and the first insulating film is formed by silicon oxide.
Preferably, the step of forming the first insulating film includes a step of flattening the first insulating film.
More preferably, the step of flattening the first insulating film is a chemical mechanical polishing step.
Preferably, in the step of doping the impurity for peeling off the first substrate, the implanting of hydrogen ions is carried out.
Preferably, the step of polishing the semiconductor layer is a chemical mechanical polishing step.
Preferably, the process further comprises, after the step of forming the first insulating film and before the step of doping the impurity for peeling off the first substrate, a step of forming a conductive film above the first insulating film and a step of forming a second insulating film above the conductive film.
More preferably, the step of forming the second insulating film includes a step of flattening the second insulating film and further preferably, the step of flattening the second insulating film is a chemical mechanical polishing step.
That is, the process of production of the semiconductor substrate comprises forming in a first substrate made of a semiconductor a groove of a predetermined depth having a predetermined pattern at an outer circumferential region of a circuit pattern of a semiconductor chip to be formed on the semiconductor layer, forming a first insulating film in the groove and above the first substrate, and flattening the first insulating film surface by chemical mechanical polishing or the like.
Next, it dopes an impurity such as hydrogen ions for peeling off the first substrate into a region of a predetermined depth of the first substrate.
Next, it bonds a second substrate from above the first insulating film and performs heat treatment to peel off the first substrate in the region with the impurity doped while leaving the semiconductor layer of the surface layer portion of the first substrate on the first insulating film.
Next, it polishes the semiconductor layer by chemical mechanical polishing or the like using as a stopper the surface of the first insulating film shaped projecting out in the bottom of the groove.
According to the process of production of the semiconductor substrate, since, as described above, the semiconductor layer is polished by using as a stopper the surface of the first insulating film shaped projected out in the bottom of the groove, reduction of the thickness of the SOI layer in accordance with the depth of the groove is possible and a thickness of for example 30 to 50 nm can be achieved.
Further, the substrate can be reused after it is peeled off, therefore the manufacturing costs can be suppressed. Further, since only a polishing variation of an amount of the thickness of the film peeled off in the peeling layer occurs and the stopper is used in the polishing as described above, variation of the SOI layer thickness can be suppressed.
Further, by forming the conductive film above the first insulating film and forming the second insulating film above the conductive film after the step of forming the first insulating film and before the step of doping the impurity for peeling off the first substrate, a semiconductor substrate of an SOI structure capable of forming a semiconductor element of a back gate structure can be manufactured.
To attain the third object, according to a third aspect of the present invention, there is provided a semiconductor device obtained from the semiconductor substrate of the first aspect of the invention.
To attain the fourth object, according to a fourth aspect of the present invention, there is provided a process of production of a semiconductor device obtained from the semiconductor substrate of the first aspect of the invention.